Embedded 3D Interposer Structure

ABSTRACT

A device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump.

This application is a continuation of U.S. patent application Ser. No. 12/823,851, filed on Jun. 25, 2010, and entitled “Embedded 3D Interposer Structure,” which application is hereby incorporated herein by reference.

TECHNICAL FIELD

This disclosure relates generally to integrated circuits, and more particularly to three-dimensional integrated circuits (3DIC) comprising interposers and the method of forming the same.

BACKGROUND

The integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.) has experienced continuous rapid increase. For the most part, the improvement in integration density has come from repeated reductions in minimum feature size, allowing more components to be integrated into a given chip area.

The integration improvement is essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limitations to the density that can be achieved in two dimensions. One of these limitations is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required. An additional limitation comes from the significant increase in the number and length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit RC delay and power consumption increase.

Three-dimensional integrated circuits (3DICs) were thus formed, wherein dies may be stacked, with wire-bonding, flip-chip bonding, and/or through-silicon vias (TSV) used to connect the dies together and to connect the dies to package substrates. The conventional 3DICs, however, have a high form factor.

SUMMARY

In accordance with one aspect, a device includes device includes an interposer, which includes a substrate; and at least one dielectric layer over the substrate. A plurality of through-substrate vias (TSVs) penetrate through the substrate. A first metal bump is in the at least one dielectric layer and electrically coupled to the plurality of TSVs. A second metal bump is over the at least one dielectric layer. A die is embedded in the at least one dielectric layer and bonded to the first metal bump.

Other embodiments are also disclosed.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1A through 1G are cross-sectional views of intermediate stages in the manufacturing of a three-dimensional integrated circuit (3DIC) in accordance with various embodiments, wherein a die is embedded in dielectric layers on a side of an interposer;

FIGS. 2A through 2C are cross-sectional views of intermediate stages in the manufacturing of a 3DIC in accordance with various embodiments, wherein a tier-1 die and the respective molding compound are bonded/applied onto an interposer before solder bumps are formed on an opposite side of the interposer;

FIGS. 3A through 3C are cross-sectional views of intermediate stages in the manufacturing of a 3DIC in accordance with various embodiments, wherein a tier-1 die (with no molding compound applied) is bonded to an interposer after solder bumps are formed on an opposite side of the interposer; and

FIGS. 4 through 6 are cross-sectional views of 3DICs in accordance with various alternative embodiments.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure.

A novel three-dimensional integrated circuit (3DIC) and the method of forming the same are provided. The intermediate stages of manufacturing an embodiment are illustrated. The variations of the embodiment are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

Referring to FIG. 1A, substrate 10 is provided. Throughout the description, substrate 10 and the corresponding dielectric layers and metal features formed on the opposite sides of substrate 10 are referred to as interposer wafer 100. Substrate 10 may be formed of a semiconductor material, such as silicon, silicon germanium, silicon carbide, gallium arsenide, or other commonly used semiconductor materials. Alternatively, substrate 10 is formed of a dielectric material such as silicon oxide. Interposer wafer 100 may include, or may be substantially free from, active devices such as transistors. FIG. 1A schematically illustrates active devices 14, which may be formed at a surface of substrate 10. Furthermore, interposer wafer 100 may include, or may be free from, passive devices such as capacitors, resistors, inductors, and/or the like. Through-substrate vias (TSVs) 20 are formed in substrate 10, and insulation layers 21 may be formed to electrically insulate TSVs 20 from substrate 10.

Redistribution lines (RDLs) 12 are formed over substrate 10, and are electrically coupled to TSVs 20. RDLs 12 may include metal lines for routing electrical signal and metal pads for landing the subsequently formed vias. In an embodiment, RDLs 12 are formed of copper, although they can also be formed of other metals such as aluminum, silver, titanium, tantalum, tungsten, nickel, and/or alloys thereof. Throughout the description, the side of interposer wafer 100 facing up in FIG. 1A is referred to as a front side, and the side facing down is referred to as a backside. Dielectric layer 18 is formed over RDLs 12, and forms a planar top surface. The materials for forming dielectric layer 18 may include nitrides, a polyimide, organic materials, inorganic materials, and the like. After the formation of dielectric layer 18, RDLs 12 are covered.

Next, as shown in FIG. 1B, die 22 is attached on dielectric layer 18, for example, through adhesive 24, with bond pads (or metal bumps) 26 facing away from dielectric layer 18. Although only one die 22 is illustrated, a plurality of identical dies 22 may be bonded to interposer wafer 100. Die 22 may be a device die comprising integrated circuit devices, such as transistors, capacitors, inductors, resistors (not shown), and the like, therein. Further, die 22 may be a logic die comprising core circuits, or a memory die. Die 22 may also be referred to as a tier-2 die hereinafter.

In FIG. 1C, dielectric layer 28 is formed over dielectric layer 18 and die 22. The materials for forming dielectric layer 28 may be essentially the same as, or selected from the same group as, that of dielectric layer 18. Dielectric layer 28 will thus comprise a first portion covering die 22, and a second portion encircling die 22. Next, as shown in FIG. 1D, vias 30, RDLs 32, and dielectric layer 34 are formed. In an exemplary formation process, via openings (filled by vias 30) are first formed in dielectric layers 18 and 28, for example, by etching, with the metal pads in RDLs 12 and bond pads 26 of die 22 acting as etching stop layers. The via openings are then filled by a metallic material to form vias 30. RDLs 32 are then formed. In alternative embodiments, vias 30 and RDLs 32 may be formed in a same metal-filling process. Dielectric layer 34 is formed over RDLs 32. Openings are then formed in dielectric layer 34, wherein the exposed portions of RDLs 32 act as bond pads. RDLs 32 may be formed of copper, although other metals such as aluminum, silver, tungsten, titanium, tantalum, and/or the like may also be used. Further, RDLs 32 may have a composite structure including a copper layer and a metal finish on the copper layer, wherein the metal finish may include a nickel layer, a palladium layer, a gold layer, or combinations thereof. Dielectric layers 18 and 28 and RDLs 12 and 32 in combinations may be referred to as an interconnect structure hereinafter.

Referring to FIG. 1E, carrier 36, which may be a glass wafer, is bonded onto the front side of interposer wafer 100 through adhesive 39, which may be an ultra-violet (UV) glue, or formed of other known adhesive materials. Next, as shown in FIG. 1F, wafer backside grinding is performed to thin substrate 10 from the backside, until TSVs 20 are exposed. An etch may be performed to further reduce the back surface of substrate 10 so that TSVs 20 protrude out of the back surface of the remaining portion of substrate 10.

As also shown in FIG. 1F, under-metal-metallurgies (UBMs) 37 and backside metal bumps 38 are formed on the backside of interposer wafer 100, and are electrically coupled to TSVs 20. Backside metal bumps 38 may be solder bumps such as eutectic solder bumps, copper bumps, or other metal bumps formed of gold, silver, nickel, tungsten, aluminum, and/or alloys thereof. The formation process may include plating, which may include electro plating or electroless plating.

It is noted that although backside metal bumps 38 are illustrated as being formed directly on TSVs 20, an additional backside interconnect structure (not shown) may be formed between, and electrically coupling, backside metal bumps 38 and TSVs 20. The backside interconnect structure may include one or more layer of RDLs, each formed in one dielectric layer.

Referring to FIG. 1G, carrier 36 is de-bonded, and another carrier (not shown) may be bonded to metal bumps 38. Bumps 46 (including bumps 46A and 46B) may then be bonded to the front side of interposer wafer 100. Bumps 46 may be solder bumps, for example, although they can also be copper bumps. Tier-1 die 44 is then bonded to interposer wafer 100 through bumps 46 using a face-to-face bonding. Although only one die 44 is illustrated, there may be a plurality of dies 44 bonded to interposer wafer 100. Tier-1 die 44 and tier-2 die 22 may be different types of dies. For example, Tier-1 die 44 may be a logic die, while tier-2 die 22 may be a memory die. It is observed that bumps 46A may be used to electrically coupling tier-1 die 44 to interposer wafer 100, while bumps 46B are used to electrically couple tier-1 die 44 to tier-2 die 22. Accordingly, dies 22 and 44 may communicate with each other directly, while the signals do not need to be routed through RDLs, TSVs, and/or the like.

After the bonding of tier-1 die 44, underfill 45 is filled into the gap between tier-1 die 44 and interposer wafer 100. A singulation may be performed on interposer wafer 100, and interposer wafer 100 is sawed apart, so that dies are separated from each other, with each of dies comprising one of dies 22 and interposer 100′ (FIG. 1G). In alternative embodiments, the singulation may be performed before bonding tier-1 die(s) 44 onto interposer wafer 100.

Next, as also shown in FIG. 1G, the 3DIC including the interposer 100′ and dies 22 and 44 are bonded to electrical component 50 through bumps 38. Electrical component 50 may be a package substrate, a printed circuit board (PCB), or the like.

FIGS. 2A through 2C illustrate an alternative embodiment. Unless specified otherwise, the reference numerals in these embodiments represent like elements in the embodiments illustrated in FIGS. 1A through 1G. The initial steps of this embodiment are essentially the same as shown in FIGS. 1A through 1D. For simplicity, some of the features such as dielectric layer 34 and UBMs 37 are not shown in subsequently discussed embodiments, although they may also be formed. Next, as shown in FIG. 2A, bumps 46 are formed, and tier-1 die 44 is bonded to interposer wafer 100. Although only one tier-1 die 44 is illustrated, a plurality of identical tier-1 dies 44 may be bonded to interposer wafer 100. Again, bumps 46A may be used to electrically couple tier-1 die 44 to TSVs 20, while bumps 46B may be used to electrically couple tier-1 die 44 to tier-2 die 22. Underfill 45 may be filled into the gap between tier-1 die 44 and interposer wafer 100. Molding compound 54 is then formed to cover tier-1 die 44 and interposer wafer 100.

FIG. 2B illustrates the formation of bumps 38, during which molding compound 54 is used as a carrier, with no additional carrier being used and attached to molding compound 54. Next, a singulation is performed to separate interposer wafer 100 (and dies 22 and 44 bonded thereon) into dies. The 3DIC is then bonded onto electrical component 50, as shown in FIG. 2C.

FIGS. 3A through 3C illustrate yet another embodiment. Again, the reference numerals in these embodiments represent like elements as in the embodiments illustrated in FIGS. 1A through 1G. The initial steps of this embodiment are essentially the same as shown in FIGS. 1A through 1D. Next, as shown in FIG. 3A, tier-1 die 44 is bonded to interposer wafer 100. Similarly, bumps 46A may be used to electrically couple tier-1 die 44 to TSVs 20, while bumps 46B may be used to electrically couple tier-1 die 44 to tier-2 die 22. Underfill 45 is then filled into the gap between tier-1 die 44 and interposer wafer 100. Compared to the embodiments shown in FIG. 2A, it is observed that no molding compound is formed in this embodiment. Next, carrier 36 is bonded to tier-1 die(s) 44. FIGS. 3B and 3C illustrate the formation of bumps 38 and the bonding of the resulting 3DIC onto electrical component 50. Again, a singulation may be performed before the step shown in FIG. 3C is performed, and the singulation may be performed with carrier 36 attached thereon, or after carrier 36 is replaced with a dicing tape (not shown).

FIGS. 4 through 6 illustrate various alternative embodiments. Referring to FIG. 4, in the embodiments in which tier-2 die 22 is not thin enough to fit in dielectric layers 18 and 28, a recess (filled by die 22 and dielectric layers 18 and 28) may be formed in substrate 10 before the formation of TSVs 20. Die 22 is located either partially or fully in the recess in substrate 10. The remaining formation processes of the 3DIC may be essentially the same as illustrated in FIGS. 1A through 3C. It is observed that in FIG. 4, some of TSVs (marked as TSVs 20A) are located directly under die 22, and RDLs 12A are electrically coupled to TSVs 20. Accordingly, the space directly under die 22 may be used to route electrical signals. Alternatively, as shown in FIG. 5, no TSV and RDL are formed directly under tier-2 die 22.

FIG. 6 illustrates yet another embodiment, wherein TSVs 60 are formed in tier-2 die 22, and electrically couple tier-1 die 44 to metal bumps 38. For example, TSVs 60 may electrically couple tier-1 die 44 to metal bumps 64, which are electrically coupled to TSVs 20A that are directly under tier-2 die 22. Metal bumps 64 may be solder bumps, copper bumps, or the like. Accordingly, a short electrical path is established to electrically couple die 22 to bumps 38, and hence the electrical performance of the resulting 3DIC is improved. It is noted in the embodiment shown in FIG. 6, a recess (not shown) similar to the recess shown in FIGS. 4 and 5 may also be formed, with die 22 being at least partially, and possibly fully, in the recess.

In the embodiments, tier-1 die 44 and tier-2 die 22 are bonded to the same side of an interposer, and hence tier-1 die 44 and tier-2 die 22 may talk directly through their direct bonding. On the other hand, with both dies 44 and 22 on a same side, the opposite side of the interposer does not have to have any die bonded thereon, and hence the number of allowed metal bumps is maximized. Furthermore, the form factor is improved.

Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure. 

What is claimed is:
 1. A method comprising: attaching a first device die onto a top surface of a substrate, wherein a plurality of TSVs extends into an intermediate level of the substrate, with the intermediate level being between the top surface and a bottom surface of the substrate; forming a dielectric layer to cover the first device die and the substrate, with bond pads of the first device die facing up; forming vias extending from a top surface of the dielectric layer into the dielectric layer, wherein the vias are electrically coupled to the bond pads of the first die and the plurality of TSVs; forming a first plurality of metal bumps over and electrically coupled to the vias; grinding a bottom side of the substrate to expose the plurality of TSVs; and forming a second plurality of metal bumps underlying and electrically coupled to the plurality of TSVs.
 2. The method of claim 1, wherein the dielectric layer has a flat top surface higher than the bond pads of the first device die, and wherein the step of forming the vias comprises etching the dielectric layer.
 3. The method of claim 1 further comprising, before the step of forming the second plurality of metal bumps, bonding a second device die to the first plurality of metal bumps.
 4. The method of claim 3 further comprising, before the step of forming the second plurality of metal bumps and after the step of bonding the second device die, molding the second device die in a molding material.
 5. The method of claim 3, wherein the vias comprise a first portion overlapping the first device die, and a second portion misaligned with the first device die, and wherein the second device die overlaps and is electrically coupled to the first portion and the second portion of the vias.
 6. The method of claim 1 further comprising bonding a package substrate to the second plurality of metal bumps.
 7. The method of claim 1 further comprising forming a recess in the substrate, wherein a portion of the first device die is located in the recess.
 8. A method comprising: forming a first plurality of through-substrate vias (TSVs) in a substrate; forming an interconnect structure comprising: forming redistribution lines over the substrate and electrically coupled to the first plurality of TSVs; forming at least one dielectric layer to cover the redistribution lines; and embedding a first die in the at least one dielectric layer; forming a first plurality of metal bumps over the interconnect structure, wherein the first plurality of metal bumps is electrically coupled to the first plurality of TSVs and the first die; forming a second plurality of metal bumps under the substrate and electrically coupled to the first plurality of TSVs; and bonding a second die to the first plurality of metal bumps.
 9. The method of claim 8 further comprising: etching the at least one dielectric layer to form via openings; and filling the via openings to form a plurality of vias comprising: a first portion electrically coupling the first plurality of metal bumps to the first die; and a second portion electrically coupling the first plurality of metal bumps to the first plurality of TSVs.
 10. The method of claim 8 further comprising bonding a package substrate to the second plurality of metal bumps.
 11. The method of claim 8 further comprising, before the step of forming the interconnect structure, etching the substrate to form a recess extending from a top surface of the substrate into the substrate, wherein the first die is at least partially located in the recess.
 12. The method of claim 8, wherein the first die comprises a second plurality of TSVs therein and electrically coupling the second die to the second plurality of metal bumps.
 13. The method of claim 8 further comprising molding a molding compound over and encircling the second die.
 14. The method of claim 8, wherein the step of bonding the second die is performed before the step of forming the second plurality of metal bumps.
 15. The method of claim 8, wherein the step of bonding the second die is performed after the step of forming the second plurality of metal bumps.
 16. A method comprising: forming a first plurality of redistribution lines (RDLs) over a substrate and electrically coupled to a first plurality of through-substrate vias (TSVs) comprised in the substrate, wherein the first RDLs comprises a metal pad; forming a first dielectric layer over the first plurality of RDLs; attaching a first die on a top surface of the first dielectric layer; forming a second dielectric layer directly over the first dielectric layer and the first die; forming a plurality of vias extending from a top surface of the second dielectric layer into the first dielectric layer, wherein the plurality of vias comprises a first via electrically coupled to the metal pad, and a second via electrically coupled to the first die; and forming a first plurality of metal bumps over and electrically coupled to the plurality of vias.
 17. The method of claim 16 further comprising, before the step of forming the first dielectric layer, recessing a portion of the substrate to form a recess in the substrate.
 18. The method of claim 16 further comprising forming a second plurality of metal bumps on an opposite side of the substrate than the first die, wherein the second plurality of metal bumps is electrically coupled to the plurality of TSVs.
 19. The method of claim 16, wherein the first die further comprises a second plurality of TSVs therein, wherein one of the first plurality of TSVs is electrically coupled to one of the second plurality of TSVs.
 20. The method of claim 16 further comprising bonding a second die to the plurality of metal bumps, wherein the first plurality of metal bumps electrically couples the first die to the second die. 